A non-volatile memory referred to as EEPROM (Electrically Erasable Programmable Random Access Memory) includes two major types; a single layer gate and a two-layer gate, depending upon the number of gates. One exemplary single layer gate is described in Japanese Laid-Open Patent Application Publication No. 6-085275 and Japanese Patent Application Publication No. Kou-Hyo 8-506693. One exemplary two-layer gate is described in Unexamined Japanese Patent Publication No. 4-080544.
FIG. 1 is a plan view illustrating an example of a conventional single layer gate non-volatile memory. A P-type semiconductor substrate (hereinafter referred to as a P-substrate) 101 has N-type diffusion regions 103, 105, 107 and a control gate 109 including N-type diffusion regions formed thereon. The N-type diffusion regions 103 and 105 are spaced from each other. The N-type diffusion regions 105 and 107 are also spaced from each other.
A select gate 111 of polysilicon is formed over the surface of the P-substrate 101 and portions of the surface of the N-type diffusion regions 103 and 105 through a gate oxide layer.
A floating gate 113 of polysilicon is continuously formed over the surface of the P-substrate 101 including the region between the N-type diffusion regions 105 and 107 and over the control gate 109 through a silicon oxide layer (not shown). In the region near the N-type diffusion regions 105 and 107, the floating gate 113 overlaps with the N-type diffusion regions 105 and 107 through a memory gate oxide layer.
In order to erase the single layer gate non-volatile memory, that is, implant electrons into the floating gate 113, the N-type diffusion region 103 is set to 0 volts, the N-type diffusion region 107 is set to a predetermined potential Vpp, and the control gate 109 and the select gate 111 are set to the predetermined potential Vpp. As a result, a select transistor including the N-type diffusion regions 103, 105 and the select gate 111 is turned ON to implant electrons from the N-type diffusion region 105 into the floating gate 113 through the memory gate oxide layer.
In order to write the single layer gate non-volatile memory, that is, emit electrons from the floating gate 113, the control gate 109 is set to 0 volts, the N-type diffusion region 107 is set into an open state, and the N-type diffusion region 103 and the select gate 111 are set to the predetermined potential Vpp. As a result, the select transistor including the N-type diffusion regions 103 and 105 and the select gate 111 is turned ON to extract electrons injected to the floating gate 113 into the N-type diffusion region 105 tunneling through the memory gate oxide layer.
In the single layer gate non-volatile memory, the control gate 109 formed by the diffusion region and the floating gate 113 of polysilicon are widely overlapped with each other on the plane of the substrate, thereby providing a high coupling ratio.
FIG. 2 is a plan view of a conventional two-layer gate non-volatile memory. N-type diffusion regions 117 and 119 are spaced on the P-substrate 101 from each other. A floating gate 123 of polysilicon is formed on a portion of the surfaces of the P-substrate 101 and portions of the surface of the N-type diffusion regions 117 and 119 through a memory gate oxide layer 121. The floating gate 123 has a control gate 127 of polysilicon formed thereon through a silicon oxide layer 125.
In order to erase the two-layer gate non-volatile memory, that is, implant electrons into the floating gate 123, the N-type diffusion region 119 is set to 0 volts, the N-type diffusion region 117 is set to a predetermined potential Vpp, and the control gate 127 is set to the predetermined potential Vpp. As a result, electrons are implanted from the N-type diffusion region 119 into the floating gate 123 through the memory gate oxide layer 121.
In order to write the two-layer gate non-volatile memory, that is, emit electrons from the floating gate 123, the control gate 127 is set to 0 volts, the N-type diffusion region 117 is set into an open state, and the N-type diffusion region 119 is set to the predetermined potential Vpp. As a result, electrons injected to the floating gate 123 are extracted into the N-type diffusion region 119 tunneling through the memory gate oxide layer 121.
All existing techniques, however, possess their own distinct disadvantages. The single-layer gate non-volatile memory provides a high coupling ratio so that memory is rewritten at relatively less voltage. However, the non-volatile memory occupies a significant with memory cell area on a substrate.
On the other hand, the two-layer gate non-volatile memory occupies less unit memory cell area on the substrate. However, its relatively small coupling ratio requires a large voltage in comparison with the single-layer gate non-volatile memory.
The semiconductor device having a non-volatile memory often includes a select transistor for a high voltage to rewrite a memory. In conventional techniques, a select transistor requires an increase in a thickness of a gate oxide layer and a double diffusion drain structure for a high breakdown voltage.
However, a high voltage of a memory-rewriting requires a long diffusion length extending in a direction of a drain depth to relieve an electric field in a high voltage transistor. In addition, the drain needs to be extracted from a region for device isolation to provide a high withstand voltage. Thus, the above-mentioned techniques have a number of these limitations which lead to a problem of an increase in the unit memory cell area.